Pulse interpolation system

ABSTRACT

A pulse interpolation system with high speed operation and improved linearity is described. An interpolation pulse train having &#39;&#39;&#39;&#39;one&#39;&#39;&#39;&#39; in all bit places is applied to the axis with the largest incremental command. On the other hand, the interpolation pulses to the other axes are obtained from a basic pulse train which is similar to a pulse train obtained by a prior DDA system. The basic pulse train is modified according to the results of the calculation of the interpolation before being applied to each related axis.

United States Patent [191 Kishi et al. Oct. 7, 1975 [54] PULSEINTERPOLATION SYSTEM 3,591,780 7/1971 Rosenfeld: 235 151. x 3,701,89010/1972 Dummermuth 235/15031 [751 Inventors: Kazush'ge 3,794,900 2/1974Kobayashietal. i. 235 151.11 x

both of Tokyo, Japan [73] Assignee: Oki Electriclndustry Co., Ltd.,Primary Examiner Malcolm Morrison Tokyo, Japan Assistant Exam'inerJerrySmith [22] Filed: June 3, 1974 Attorney, Agent, or FirmKenyon & KenyonAppl. No.: 475,852

Foreign Application Priority Data June 5, 1973 Japan 48-62595 US. Cl.235/15l.11; 235/150.31; 235/152;

318/573 Int. Cl. G06F 15/46 Field of Search 235/150.3l, 151.11, 152'References Cited UNlTED STATES PATENTS Hoernes 235/l5l.ll

[57] ABSTRACT A pulse interpolation system with high speed operation andimproved linearity is described. An interpolation pulse train having onein all bit places is applied to the axis with the largest incrementalcommand. On the other hand, the interpolation pulses to the other axesare obtained from a basic pulse train which is similar to a pulse trainobtained by a prior DDA system. The basic pulse train is modifiedaccording to the results of the calculation of the interpolation beforebeing applied to each related axis.

2 Claims, 6 Drawing Figures US Patent cm. 7,1975 Sheet 1 of 3 3,911,258

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lx AX I AI RX PM) RY L QB P(Y) IY AY Fig. NB)

RX RY rn r fOVF .L 6 3%? MPH AI 1 4 8 1 4 8 P00 PM mmhmamm Sheet 2 0f 3Oct. 7,1975

mmjm F 52 US. Patent U.S. Patent 001. 7,1975 Shee1 3 of3 3,911,258

H'g.5(B)

Fig. 4 YAX AY, AM N, i=10. B=7

PULSE INTERPOLATION SYSTEM BACKGROUND OF THE INVENTION The presentinvention relates to a pulse interpolation 5 system and, in particular,relates to an improved pulse interpolation system which provides manyinterpolation pulses in a short time with high efficiency.

A pulse interpolation system is utilized in numerical controlled (N.C.)devices, including a positioning system or a contouring control system,and digital X-Y plotter and automatic drawing machine and a graphicdisplay device et al. The interpolation pulses control the drivingmeans, such as a pulse motor, in NC. devices or X-Y plotter andautomatic drawing machine and a graphic display device. In order toobtain rapid operation of NC. devices or X-Y plotter and automaticdrawing machine and a graphic display device, rapid interpolation pulsesare necessary.

There have previously been known at least two pulse interpolationsystems. One is a DDA (Digital Differential Analyzer) system, in whichan adder for the X axis accepts an increment command AX and provides theoutput signal I or 0 in accordance with the overflow of the adder fromthe addition. However, the DDA system has the disadvantage that eachaddition provides only one interpolation pulse and the operational speedof driving means is fairly slow.

The other prior pulse interpolation system is shown in the articleewntitled, A Software Interpolation Scheme for Direct Numerical Control,by Donard Wortzman, in I970 NCS Proceedings Seventh Annual Meeting andTechnical Conference. According to this prior art, a desirable pulsetrain is stored in the tables of a digital memory for every decimalfigure and by reading said pulses from said memory, the interpolationpulses are provided. In order to obtain high speed pulses, said tablesshould have as many as possible one" (not zero) elements, and for thatpurpose the following normalization process is performed.

where AX, is an incremental command for the X axis, A), is anincremental command for the- Y axis, AX is a normalized incrementalcommand for the X axis, AY is a normalized incremental command for the Yaxis, K is a constant, 11, is a number of output pulses for one axisbefore the normalization and n is a number of outand the values of theleast two significant digits of Kn, must be zero. The process of theabove normalization is fairly complicated.

SUMMARY OF THE INVENTION It is an object, therefore, of the presentinvention to overcome the disadvantages and limitations of the priorpulse interpolation systems by providing a new and improved pulseinterpolation system.

It is also an object of the present invention to provide a new andimproved pulse interpolation system with high speed operation andimproved linearity.

The above and another objects are attained by a pulse interpolationsystem comprising the steps of:

selecting PN and PN, from all incremental commands, where PN is thelargest incremental command, and PN, is one other than PN multiplying PNand i by means of a first multiplier, where i is a number ofinterpolation pulses obtained in each operational cycle;

dividing said product of PN times i by PN by means of a first divider;

dividing PN by i by means of a second divider;

multiplying OPN and NR, by means of a second multiplier, where OPN is aquotient of said first divider, and NR, is a remainder of said seconddivider;

dividing the product of OPN times NR, by i by means of a third divider;

adding AMR and A by means of an adder, where AMR, is a remainder of saidfirst divider and A is a remainder of said third divider;

dividing the sum (AMR A) by i by means of a fourth divider;

comparing AM with N, where AM is a quotient of said fourth divider and Nis a quotient of said second divider;

providing a basic pulse train according to said values of OPN, and 1';

adding a value of AM in a variable capacity register if N is equal to orlarger than AM according to said comparison;

adding a value of (AM-l in a variable capacity register if N is smallerthan AM according to said comparison, where the capacity of the variablecapacity register is equal to N;

modifying said basic pulse train by inserting one" in said pulse trainby an overflow pulse of said variable eapaeity register;

providing a pulse train having one in all bit places to an axis with thelargest incremental command as interpolation pulses, and;

providing said modified basic pulse train to the corresponding axis asinterpolation pulses.

BRIEF EXPLANATION OF THE DRAWINGS FIG. 1(A) is a block diagram of aprior DDA system;

FIG. 1(B) is an explanatory drawing of FIG. 1(A);

FIG. 2 is a block diagram of a pulse interpolation system according tothe present invention;

FIG. 3(A) and FIG. 3(B) are an exemplary curve and a pair ofinterpolation pulse trains, respectively, according to the apparatus ofFIG. 2, and;

FIG. 4 is another example of a pair of pulse trains according to thepresent invention.

PREFERRED EMBODIMENTS FIG. 1(A) shows a block diagram of a prior DDA(Digital Differential Analyzer). In FIG. 1(A), an incremental command AX(or AY) is stored in a register I, (or Iy) as an adder, and the commandis accumulated in a register R, (or Ry) each time the addition commandAI is applied. If an overflow occurs in the register R, (or Ry) due tothe addition, an interpolation pulsel P(X) or P(Y) is obtained from theregister R, (or R,-). FIG. 1(B) shows the operation of FIG. 1(A). It isassumed that registers I and I,', and accumulators R, and R, have threehits respectively, and that incremental commands AX and AY are 011 and101, respectively. The accumulator R, or R,- overflows each time itscontent reaches eight, and an interpolation pulse P(X) or P(Y) isobtained as shown in FIG. 1(B). Through above operation, threeinterpolation pulses P(X) and five interpolation pulses P(Y) areobtained. However,

as mentioned above, the DDA system has a disadvan tage that only oneinterpolation pulse is obtained by each addition.

FIG. 2 shows a block diagram of a pulse interpolation system accordingto the present invention, which overcomes the disadvantages of the priorarts. In FIG. 2,

CP, and CP are comparators; G,, G G;,, G,, G G G G,, and G are ANDcircuits; M, and M are multipliers; D,, D D and D are dividers; HD is ahalf multiplier; T is a converter; R,, R R R and R,-, are registers; Pis a feed-pulse generator; SR, and SR,, are shift registers; C, and Care counters; I is a reference signal generator, the content i of whichdefines a number of output pulses obtained in one operational cycle; ADis an adder, and; AX and AY are values of incremental commands.

The operation of the apparatus of FIG. 2 will now be explained. For thesake of simplicity of the explanation, a numerical embodiment wherein AX23, AI and i= 10, is explained with the following operationalexplanation.

The comparator CP, compares a value of AX with a value of AY, andprovides an output signal on a line L when the value of AX is largerthan or equal to the value of AY, or provides an output signal on a line1 when the value of AX is smaller than the value of AY. The line L isconnected to the inputs of AND circuits G G G, and G and the line I isconnected to the inputs of ANd circuits G,, (3,, G and G,,. These ANDcircuits are opened when a signal on the line L or line I is provided.Accordingly, if AX 5 A), a larger incremental value AX is appliedthrough the ANd circuit G to a first divider D, as a divisor s, a seconddivider D; as a dividend t, and a counter C as a preset 'number. Asmaller incremental value AY is applied to an input of a firstmultiplier M, through the AND circuit G On the other hand, if AX AY, alarger incremental value AY is applied through the AND circuit G, to thefirst divider D, as the divisor s, and the second divider D the dividendt, and the counter C as a preset number, and a smaller incremental valueAX is applied to an input of the first multiplier M, through the ANDcircuit 0,. The dividers D,, D D and D, are integer type dividers, eachof which receives a dividend at an input I and a divisor at an input sand provides a quotient at an output 0 and a remainder at an output R.

In the present embodiment, since AX is 23 and AY= 20, AX is larger thanAY (AX A Accordingly, the second .divider D receives the largerincremental command PN AX= 23) as a dividend at the input I, and l' l())as a divisor at the input s. and performs the division and provides aquotient N 2) at an output Q and a remainder NR 3) at an output R. Saidquotient N 2) is applied to a half multiplier HD which provides anoutput (1) which is half of an input (2) to a register R for pro-settingthe same to 1/2 N I).

Said quotient N is also applied to a register R, and a counter C, forpre-setting them to N 2), and one input of a comparator CP The halfmultiplier HD works for improving the accuracy of the interpolation, Theremainder NR 3) at the output R of said second divider D is applied tothe first input of the second multiplier M A smaller incremental commandvalue PN,,-( A) 20) is applied to the first input of the firstmultiplier M, through the AND circuit 0,. The second input of said firstmultiplier M, is supplied the value of i 10) from the reference signalgenerator I. The first multiplier M, performs the multiplication AYtimes i 20 X 10), and its product 200) is applied to the input t of thefirst divider D as a dividend. The first multiplier M, and the firstdivider D, compose the first arithmetic means 11. The first divider D,performs the division (AYXi The quotient ()PN 8) of said division isapplied to the first input of the second multiplier M and the firstinput of the converter T from the output Q of said first divider D,. Theremainder AMR, 16) of said division is applied to the first input of theadder AD from. the output R of said first divider D,. The secondmultiplier M receives the quotient OPN 8) from the first divider D, andthe remainder NR 3) from the second divider D and performs themultiplication OPN times NR, 8 X 3 24). The product of saidmultiplication is supplied as a dividend to the third divider D whichreceives also the divisor i from the reference signal generator I. Thethird divider D performs the division (01W,- NR (8 x 3 and its remainderA 4) is applied to the second input of the adder AD from the output R ofthe divider D,,. The dividers D D and the multiplier M compose thesecond arithmetic means 12.

The adder AD receives the remainder AMR 16) from the first divider D,and the remainder A 4) from the third divider D and performs theaddition AMR plus A 16 +4= 20). The sum 20) ofsaid addition is appliedas a dividend to the fourth divider D,. which receives the divisor ifrom the reference signal generator I. The quotient AM 2) of thedivision by said fourth divider D, is applied to the second input of thecomparator CP Said adder AD and the divider D, compose the thirdarithmetic means 13.

The converter T provides one of the following pulse trains according tothe input signal from the divider D, on the condition that the value ofi from the reference signal generator I is 10.

Input to the Convener T Output pulse trains from the Converter T BitNumber (l 101 l l l The pulse trains in above table are the same as aseries of overflow pulses from an accumulator which adds an input numberto the content of itself and produces an overflow pulse every time itscontent exceeds the predetermined number i 10). That is to say, theconverter T provides parallelly the same'pulse trains as those from aconventional DDA (Digital Differential Analyzer). 1n the presentembodiment, since the value ofi is 10 and an input number to theconverter which is-the same as a quotient OPN of the divider D, is 8,the converter T outputs a pulse train (0 l l l l O l 1 l l according tothe above table, and the output pulse train' from the converter T isstored in a register R, The pulse train stored in the register R iscalled a basic pulse train B. On the other hand, a register R stores aseries of pulse train, all bits of which are one, and the bit length ofthe register R is defined by the value of i In the present embodiment,the content of the registcrR,-,is(lllll11111).

The comparator CP receives two inputs, one is a quotient AM from thefourth divider D, and the other is a quotient N from the second dividerD and according to the result of the comparison of the two inputs, itoperates as follows.

a. When N 2 AM, and N a 0.

In this case, l a value of AM is pre-set in the register R through aline a, (2) the content of said register R after the above pre-settingis added by the control through a line b, to the content of the registerR whose initial content is equal to the output of the half multiplierHD, and (3) through a line c, an AND circuit G is provided a zero input.

b. When N AM, and N 0,

In this case, l a value of (AM l is pre-set in the register R throughthe line a, (2) the content of said register R after the abovepre-setting is added to the content of the register R and (3) throughthe line 0, the AND circuit (3| is provided a one input.

c. When N =0,

In this case, l the register R is not loaded, in other words, thecontent of the register R becomes zero, and (2) the AND circuit 6,, isprovided a one input.

The register R is a variable capacity register, whose capacity is equalto the content of the register R,, and after adding the content of theregister R and the register R the register R provides an overflow pulsewhen the result of the addition of the registers R and R exceeds saidcapacity content of the register R,) defined by the register R,. Whenthe register R over flows, the content of the first bit of the registerR, is changed to one, otherwise it is not changed.

ln the-present embodiment, the value of AM is 2, and the value of N is2, consequently, AM is equal to N (AM N). The initial value of theregister R is l (which is the same as the content of the half multiplierHD), and the capacity of the register R is 2 (which is the same as thecontent of the register R,). Therefore, according to item (a) above, theregister R is loaded with the value of AM 2), which is added to thecontent of the register R the sum of which is 3 l 2). Since the capacityof the register R is only 2, the register R overflows, and provides anoverflow pulse. The content of theregister R after the overflow is l 32). Since the register R overflows, the first bit of the register R ischanged to l and, thus, the content of the register R becomes l l l l lO l l l l although the original content of the same is O l l l l 0 l l.l l

The contentsof the registers R and R are transferred to shift registersSR, and SR through AND circuits G and G,,, or through ANd circuits 6,,and (3,. In the present-embodiment, since AX is larger than AY, thecomparator CP, opens AND circuits 0,, and 0,. Accordingly, the contentof the register R, is transferred to the'shift register SR and thecontent of the register R,-, is transferred to the shift register SR,.When said transfer is completed, the content of the counter C, (whoseinitial content is 2), is reduced by one. At this time, the contents ofthe shift registers SR, and SR are(1lllllllll)and(ll1ll()llll),respectively.

The feed pulse generator P causes the shift register SR, to send aseries of interpolation pulses for the X axis, and the shift' registerSR for the Y axis. When all pulses stored in shift registers SR, and SRhave beenn sent to the X and Y axes, the feed pulse generator P causesthe registers R, and R to transfer their contents to shift registers SRand SR, through AND circuits 6;, through G,,. At the same time, the feedpulse generator P applies a feed pulse to the counter C (whose initialcontent is 23) causing a reduction of the content of the counter C byone. The above operation is repeated until the content of the counter C-reaches zero. When the content of the counter C reaches zero, thecounter C provides an end signal E, which causes the termination of thepulse interpolation operation of the present system. It is apparent fromthe above explanation that the interpolation pulses l l l l l l 1 l l lare sent to the X axis and the interpolation pulses l l l 1 l 0 l 1 1 lare sent to the Y axis during the first operational cycle.

Next, the operation of the counter C, is explained. The counter C, isinitially loaded with the quotient N of the second divider D Accordingto a value of N, the counter C, works as follows.

a. When N is zero, a signal is applied from the output terminal Z of thecounter C, to the AND circuit G,,. Since the comparator CP- applies asignal to the AND circuit G as explained before, in case of N 0, the ANDcircuit G provides an output signal to the register R The output signalfrom the AND circuit G causes the register R to change the first bit ofthe register R to one.

b. When N is not zero, the counter C, provides no output signal.

As explained before, the content of the counter C, is reduced by onewhen the data transfer from thhe registers R, and R to the shiftregisters SR, and SR is completed. According to the content (C of thecounter C after said reduction, the counter C works as follows.

a. When (C is not zero, (C 0, a command for addition is applied from theoutput terminal M of the counter C, to the register R and the content ofthe register R is added to the content of the register R If an overflowoccurs as a result of that addition in the register R the first bit ofthe register R is changed to one, otherwise it remains zero, asexplained before.

b. When (C is zero, (C 0, no addition is performed, but a signal isprovided to the AND circuit G from the output terminal Z of the counterC Therefore, if the comparator CP is applying a signal to the ANDcircuit G said AND circuit G provides an output signal, which changesthe first bit in the register R to one, otherwise said first bit remainszero.

In the present embodiment AX= 23, AY= 20), the interpolation pulsesobtained from the shift registers SR and SR are as follows.

1. In the first operational cycle, the interpolation pulses for the Xaxis and the Y axis are l l l l l l llll)and(lll1101111),respectively,asexplained before.

2. In the second operational cycle, the interpolation pulses for the Xaxis and the Y axis are l 1 l 1 l ll1ll)and(lll1lOll11),respectively.The reason for this is that after thereduction the content of the counter C is one and not zero.

Therefore, the content of the register R 2) is added to the content ofthe register R (whose initial content is 1), according to the above item(a) and an overflow occurs since the capacity of the register R is only2. Then, the first bit of the register R whose original content is( l ll 1 0 l 1 l 1 )from the above table, is changed to one and, thus, thecontent of the register R becomes 1 l l l l 0 l l l I On the other hand,the register R is loaded with l l l 1 l l l l l l by the referencesignal generator I through the converter T.

3. In the third operational cycle, the interpolation pulses for the Xaxis and the Y axis are l l l and 0 l l respectivcley. In this cycle,the content of the counter C after the reduction is zero, and thecounter C applies a signal to the AND circuit G However, the comparatorCP does not apply a signal to the AND circuit G since both the quotientsAM and N are 2 and equal each other. Therefore. the AND circuit G doesnot provide an output signal, and the first bit of the register R is notchanged. Thus, the content of the register R remains 0 1 l l l 0 1'1 1 lOn the other hand. the content of the register R is l l 1 1 l l l l 1 1When the first three bits 1 l 1 and 0 1 l are transferred asinterpolation pulses from the shift registers SR and SR to thecorresponding axis, the content of the counter C reaches zero and thepulse interpolation operation is terminated.

FIG. 3(A) shows a curve of a moving path of, for instance, a bit of anumerical control machine, where AX 23, AY and 1' 10. FIG. 3(B) showsthe pulse trains for the X axis and the Y axis on the same conditionabove. As apparent from FIGS. 3(A) and 3(8), interpolation pulses areapplied without interruption to the X axis which is given the largercommand. (That is to the output signal to the X axis is one in all bitplaces in this embodiment). Accordingly, the present invention improvesinterpolation speed and the linearity of a moving path.

FIG. 4 shows another embodiment of pulse trains where AX AY, AM 5 N, i=l0 and B (the number of pulses in a cycle in a basic pulse train) is 7.

Although, the embodiment having only two axes is explained above, thepresent invention is applicable to the interpolation system having morethan three axes. When the system has more than three axes, the divider Dshould be supplied the largest incremental command as a dividend.

Most of the parts of the device shown in FIG. 2 can be replaced by ageneral purpose computer having appropriate software. In that case, asimple peripheral circuit 14 having the shift registers SR and SR a feedpulse generator P, and a counter C need only be connected to theprogrammed computer.

As is apparent from the above explanation, the present invention has aparticular advantage in that many interpolation pulses with high speedcan be obtained in a short time. Therefore, the present invention isapplicable to a CNC (Computer NC) system, a numerical controlled machinetool with high speed operation, and the interpolation system between twopoints such as a X-Y plottere, and automatic drawing machine and agraphic display device. Since one particular axis is always providedwith interpolation pulses according to the present invention, thepresent invention is very useful for those systems having another axiswhich operates in a corresponding manner to said particular axis, suchas a numerical controlled screw cutter.

From the foregoing, it will now be apparent that a new and improvedpulse interpolation system has been found. It should be understood, ofcourse, that the embodiments disclosed are merely illustrative and arenot intended to limit the scope of the invention. Reference should bemade to the following claims for an indication of the scope of theinvention.

Finally, the major reference numbers and symbols used herein are listedbelow.

C P,, C P Comparator M M multiplier D,-D divider HD half multiplier Tconverter P feed pulse generator SR SR Shift register C C Counter Ireference signal generator AX, AY, incremental command AD adder 1 Ifirst arithmetic means 12 second arithmetic means 13 third arithmeticmeans l4 peripheral circuit What is claimed is: g

l. A pulse interpolation system comprising:

a. a first arithmetic means having a first multiplier for themultiplication i times PNs, and a first divider for the division of theproduct (ixPNs) of said multiplication by PN where i is an integerrepresenting a number of pulses to be interpolated in one operationalcycle, PNs is an integer representing an incremental command for theaxis other than that having the largest incremental command, and PN isan integer representing the largest incremental command;

b. a second arithmetic means having a second divider for the division PN/i,

a second multiplier for the multiplication OPNs times NR,,, and a thirddivider for the division of the product of said second multiplier by i,where OPNs is a quotient of said first divider and NR is a remainder ofsaid second divider;

c. a third arithmetic means having an adder for AMRs plus A, and afourth divider for the division of the sum of said adder by i, whereAMRs is a remainder of said first divider and A is a remainder of saidthird divider;

d. a variable capacity register with capacity N where N is a quotient ofsaid second divider;

e. a converter for obtaining the particular basic pulse train defined bythe value of OPNs, and for changing a value of i to a pulse train havingone in all bit places;

f. means for adding a value of AM in said variable capacity register ifN is equal to or larger than AM, and adding a value of (AM-l) in thesame if N is smaller than AM, where AM is a quotient of said fourthdivider, and N is a quotient of said second divider;

g. means for modifying said basic pulse train by inserting a pulse insaid basic pulse train according to an overflow pulse from said variablecapacity register due to said addition;

h. means for providing said modified pulse train to the related axis anda pulse train having one in all bit places to the axis of the largestincremental command, and;

i. counter for counting the output interpolation pulses for terminatingthe operation of the present system.

2. A method for providing an interpolation pulse comprising the stepsof:

a. selecting PN and PNs from all incremental commands where PN is thelargest incremental command, and PNs is one other than PN b. multiplyingPNs and i by means of a first multiplier, where i is a number ofinterpolation pulses obtained in each operational cycle;

c. dividing said product PNs x i by PN by means of a first divider;

d. dividing PN by i by means of a second divider;

e. multiplying OPNs and NR by means of a second multiplier, where OPNsis a quotient of said first divider, and NR is a remainder of saidsecond divider;

f. dividing the product OPNs X NR by i by means of a third divider;

g. adding AMRs and A by means of an adder, where AMRs is remainder ofsaid first divider and A is a remainder of said third divider;

h. dividing the sum (AMRs A) by 1' means of a fourth divider;

i. comparing AM with N, where AM is a quotient of said fourth dividerand N is a quotient of said second divider;

j. providing a basic pulse train according to said values of OPNs and i;

k. adding a value of AM in a variable capacity register if N is equal toor larger than AM according to said comparison;

. adding a value of (AM-l) in a variable capacity register if N issmaller than AM according to said comparison, where the capacity of thevariable capacity register is equal to N;

m. modifying said basic pulse train by inserting one in said pulse trainby an overflow pulse of said variable capacity register;

n. providing a pulse train having one in all bit places to an axis withthe largest incremental command as interpolation pulses;

0. providing said modified basic pulse train to its corresponding axisas interpolation pulses, and;

p. counting the number of pulses from a feed pulse generator forterminating the operation of the pulse interpolation system.

1. A pulse interpolation system comprising: a. a first arithmetic meanshaving a first multiplier for the multiplication i times PNs, and afirst divider for the division of the product (ixPNs) of saidmultiplication by PNL, where i is an integer representing a number ofpulses to be interpolated in one operational cycle, PNs is an integerrepresenting an incremental command for the axis other than that havingthe largest incremental command, and PNL is an integer representing thelargest incremental command; b. a second arithmetic means having asecond divider for the division PNL/i, a second multiplier for themultiplication OPNs times NRL, and a third divider for the division ofthe product of said second multiplier by i, where OPNs is a quotient ofsaid first divider and NRL is a remainder of said second divider; c. athird arithmetic means having an adder for AMRs plus A, and a fourthdivider for the division of the sum of said adder by i, where AMRs is aremainder of said first divider and A is a remainder of said thirddivider; d. a variable capacity register with capacity N where N is aquotient of said second divider; e. a converter for obtaining theparticular basic pulse train defined by the value of OPNs, and forchanging a value of i to a pulse train having one in all bit places; f.means for adding a valuE of AM in said variable capacity register if Nis equal to or larger than AM, and adding a value of (AM-1) in the sameif N is smaller than AM, where AM is a quotient of said fourth divider,and N is a quotient of said second divider; g. means for modifying saidbasic pulse train by inserting a pulse in said basic pulse trainaccording to an overflow pulse from said variable capacity register dueto said addition; h. means for providing said modified pulse train tothe related axis and a pulse train having one in all bit places to theaxis of the largest incremental command, and; i. counter for countingthe output interpolation pulses for terminating the operation of thepresent system.
 2. A method for providing an interpolation pulsecomprising the steps of: a. selecting PNL and PNs from all incrementalcommands where PNL is the largest incremental command, and PNs is oneother than PNL; b. multiplying PNs and i by means of a first multiplier,where i is a number of interpolation pulses obtained in each operationalcycle; c. dividing said product PNs x i by PNL by means of a firstdivider; d. dividing PNL by i by means of a second divider; e.multiplying OPNs and NRL by means of a second multiplier, where OPNs isa quotient of said first divider, and NRL is a remainder of said seconddivider; f. dividing the product OPNs X NRL by i by means of a thirddivider; g. adding AMRs and A by means of an adder, where AMRs isremainder of said first divider and A is a remainder of said thirddivider; h. dividing the sum (AMRs + A) by i means of a fourth divider;i. comparing AM with N, where AM is a quotient of said fourth dividerand N is a quotient of said second divider; j. providing a basic pulsetrain according to said values of OPNs and i; k. adding a value of AM ina variable capacity register if N is equal to or larger than AMaccording to said comparison; l. adding a value of (AM-1) in a variablecapacity register if N is smaller than AM according to said comparison,where the capacity of the variable capacity register is equal to N; m.modifying said basic pulse train by inserting one in said pulse train byan overflow pulse of said variable capacity register; n. providing apulse train having one in all bit places to an axis with the largestincremental command as interpolation pulses; o. providing said modifiedbasic pulse train to its corresponding axis as interpolation pulses,and; p. counting the number of pulses from a feed pulse generator forterminating the operation of the pulse interpolation system.